US 12,354,939 B2
Multi-role semiconductor device substrates, semiconductor device assemblies employing the same, and methods for forming the same
Hong Wan Ng, Singapore (SG); Chin Hui Chong, Singapore (SG); Kelvin Tan Aik Boo, Singapore (SG); and Seng Kim Ye, Singapore (SG)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 3, 2022, as Appl. No. 17/686,225.
Prior Publication US 2023/0282559 A1, Sep. 7, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/552 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4846 (2013.01); H01L 23/49816 (2013.01); H01L 23/552 (2013.01); H01L 24/08 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 24/80 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/49112 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06562 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device assembly comprising:
a printed circuit board (PCB) substrate including:
an upper surface on which is disposed a first device contact,
a keep-out region extending from a first side surface of the substrate to a second side surface of the substrate opposite the first, and
at least one trace coupled to the first device contact and extending across the keep out region towards a third side surface of the substrate; and
at least one semiconductor device disposed over the upper surface of the substrate and coupled to the first device contact,
wherein the keep-out region of the substrate is free from conductive structures other than the at least one trace,
wherein the at least one trace is exposed at the third side surface of the substrate, and
further comprising an electromagnetic interference (EMI) shield electrically coupled to the exposed at least one trace at the third side surface of the substrate.