US 12,354,938 B2
Semiconductor package and methods of manufacturing
Hsien-Wei Chen, Hsinchu (TW); Meng-Liang Lin, Hsinchu (TW); and Shin-Puu Jeng, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 6, 2022, as Appl. No. 17/662,366.
Prior Publication US 2023/0361016 A1, Nov. 9, 2023
Int. Cl. H01L 23/49 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49838 (2013.01) [H01L 21/4853 (2013.01); H01L 23/367 (2013.01); H01L 23/49816 (2013.01); H01L 23/49833 (2013.01); H01L 23/49894 (2013.01); H01L 25/0655 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/3512 (2013.01); H01L 2924/37001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate comprising a top surface;
an interposer comprising a bottom surface facing the top surface of the substrate;
an integrated circuit die electrically connected to a bottom surface of the interposer;
a spacer structure mechanically connected to the bottom surface of the interposer,
wherein the spacer structure is disposed beside the integrated circuit die, a first distance between the spacer structure and the substrate is no more than a second distance between the integrated circuit die and the substrate, and
wherein the first distance is included in a range of approximately 1 micron to approximately 20 microns; and
a plurality of connection structures electrically connecting the substrate and the interposer.
 
11. A method, comprising:
forming a spacer structure on a bottom surface of an interposer,
wherein forming the spacer structure comprises forming a bottom surface of the spacer structure at a first distance from the bottom surface of the interposer;
attaching an integrated circuit die to the bottom surface of the interposer,
wherein attaching the integrated circuit die to the bottom surface of the interposer comprises positioning a bottom surface of the integrated circuit die at a second distance from the bottom surface of the interposer, and
wherein the second distance is lesser relative to the first distance; and
attaching a substrate to the bottom surface of the interposer,
wherein attaching the substrate to the bottom surface of the interposer comprises positioning a top surface of the substrate at a third distance from the bottom surface of the interposer, and
wherein the third distance is greater relative to the first distance by a distance of approximately 1 micron to approximately 20 microns.
 
16. A semiconductor structure comprising:
an interposer that comprises a bottom surface;
a spacer structure electrically and/or mechanically connected to the bottom surface of the interposer,
wherein the spacer structure comprises a bottom surface at a first distance from the bottom surface of the interposer;
an integrated circuit die electrically and mechanically connected to the bottom surface of the interposer,
wherein the integrated circuit die comprises a bottom surface at a second distance from the bottom surface of the interposer that is lesser relative to the first distance; and
a substrate comprising a top surface that is electrically or mechanically coupled to the bottom surface of the interposer,
wherein the top surface of the substrate and the bottom surface of the spacer structure are separated by a clearance included in a range of approximately 1 micron to approximately 20 microns.