US 12,354,937 B2
Semiconductor device and production method thereof
Takao Kasai, Kariya (JP)
Assigned to DENSO CORPORATION, Kariya (JP)
Filed by DENSO CORPORATION, Kariya (JP)
Filed on Jul. 8, 2021, as Appl. No. 17/370,770.
Application 17/370,770 is a continuation of application No. PCT/JP2019/049879, filed on Dec. 19, 2019.
Claims priority of application No. 2019-002913 (JP), filed on Jan. 10, 2019.
Prior Publication US 2021/0335700 A1, Oct. 28, 2021
Int. Cl. H01L 23/498 (2006.01); H01L 21/60 (2006.01)
CPC H01L 23/49838 (2013.01) [H01L 21/60 (2021.08); H01L 23/49811 (2013.01); H01L 2021/60007 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor package which is equipped with a plurality of electrodes; and
a mount member which is equipped with a plurality of lands and on which the semiconductor package is mounted, wherein:
the semiconductor package has the electrodes joined to the lands through solders,
at least a subset of the electrodes work as position/orientation control electrodes to control a position and orientation of the semiconductor package relative to a mount surface that is a surface of the mount member which faces the semiconductor package,
at least a subset of the lands work as position/orientation control lands to control the position and orientation of the semiconductor package relative to the mount surface of the mount member,
each of the position/orientation control electrodes is arranged in a planar view thereof to have a center thereof offset from a center of a respective one of the position/orientation control lands which is joined to the position/orientation control electrode through the solder, each of the position/orientation control electrodes lying inside an outline of a corresponding one of the position/orientation control lands
the number of position/orientation control lands and the number of position/orientation control electrodes are plural,
each of the position/orientation control electrodes is exposed outside only a lower surface of the semiconductor package which faces the mount member,
each of the position/orientation control lands is arranged in a planar view thereof in a region located inside an outline of the semiconductor package,
a direction from the center of each of the position/orientation control electrodes to the center of a corresponding one of the position/orientation control lands is defined as an offset direction toward a center of the semiconductor package in a planar view thereof, a spread of each of the position/orientation control lands relative to a corresponding one of the position/orientation control electrodes becomes larger in the offset direction than in a direction opposite the offset direction,
each of the position/orientation control lands and a respective one of the position/orientation control electrodes which are joined together through one of the solders are defined as a position/orientation control pair, the position/orientation control pairs being arranged to be symmetrical with respect to the center of the semiconductor package in the planar view thereof,
each solder of the solders between all of the position/orientation control electrodes and all of the position/orientation lands is arranged in the planar view thereof only inside an outline of the semiconductor package, and
the position/orientation control electrodes are arranged to have portions of outlines thereof which are at least located far away in the direction opposite the offset direction and coincide with outlines of the position/orientation control lands joined to the position/orientation control electrodes through the solders in a planar view thereof.