US 12,354,924 B2
Integrated circuit package and method
Chien-Hsun Chen, Zhutian Township (TW); Yu-Ling Tsai, Hsinchu (TW); Jiun Yi Wu, Zhongli (TW); Chien-Hsun Lee, Chu-tung Town (TW); and Chung-Shi Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 10, 2024, as Appl. No. 18/631,966.
Application 18/631,966 is a continuation of application No. 18/302,589, filed on Apr. 18, 2023, granted, now 11,984,375.
Application 18/302,589 is a continuation of application No. 17/567,519, filed on Jan. 3, 2022, granted, now 11,658,085, issued on May 23, 2023.
Application 17/567,519 is a continuation of application No. 16/882,995, filed on May 26, 2020, granted, now 11,217,497, issued on Jan. 4, 2022.
Application 16/882,995 is a continuation of application No. 16/173,488, filed on Oct. 29, 2018, granted, now 10,665,520, issued on May 26, 2020.
Prior Publication US 2024/0258187 A1, Aug. 1, 2024
Int. Cl. H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/3121 (2013.01) [H01L 23/49827 (2013.01); H01L 23/5384 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of integrated circuit dies, each die having a top surface with a contact region populated with die connectors and a non-contact region free of die connectors;
an encapsulant material encapsulating sides of the integrated circuit dies;
a dielectric layer over the encapsulant material and the integrated circuit dies;
a metallization pattern on the dielectric layer, the metallization pattern including:
conductive vias extending through the dielectric layer to electrically connect with the die connectors;
conductive lines interconnecting the conductive vias, wherein the conductive lines comprise:
straight portions over the encapsulant material between adjacent integrated circuit dies; and
meandering portions over the non-contact regions of the integrated circuit dies, the meandering portions configured to absorb mechanical stress and to facilitate electrical connection between widely spaced die connectors; and
dummy conductive features at least partially around the conductive vias and along the conductive lines.