| CPC H01L 22/32 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 24/05 (2013.01); G01R 1/0491 (2013.01); H01L 21/76816 (2013.01); H01L 24/08 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08147 (2013.01); H01L 2924/30101 (2013.01)] | 6 Claims |

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1. A wafer structure, comprising:
a substrate structure;
a first dielectric layer disposed on the substrate structure;
a plurality of test pads disposed in the first dielectric layer and exposed outside the first dielectric layer, wherein each of the test pads has a probe mark;
a second dielectric layer disposed on the first dielectric layer and having a top surface away from the test pads; and
a plurality of bond pads disposed in the second dielectric layer and exposed outside the second dielectric layer, wherein each of the bond pads is electrically connected to a corresponding test pad, the bond pads have bonding surfaces away from the test pads, and the bonding surfaces are flush with the top surface,
wherein in a normal direction of the substrate structure, each of the bond pads does not overlap with the corresponding probe mark of the test pad,
wherein the test pads are electrically connected to the substrate structure, and the test pads are not electrically connected to one another,
wherein the second dielectric layer is further disposed in the probe mark.
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