US 12,354,918 B2
Package geometries to enable visual inspection of solder fillets
LongTing Li, ChengDu (CN); and HuoYun Duan, ChengDu (CN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 30, 2021, as Appl. No. 17/491,405.
Prior Publication US 2023/0098907 A1, Mar. 30, 2023
Int. Cl. H01L 21/304 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01); H05K 3/34 (2006.01)
CPC H01L 22/14 (2013.01) [H01L 21/304 (2013.01); H01L 24/85 (2013.01); H01L 24/96 (2013.01); H01L 24/97 (2013.01); H05K 3/3405 (2013.01); H05K 3/3457 (2013.01); H01L 2224/85801 (2013.01); H01L 2224/85986 (2013.01); H05K 2203/162 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor package, comprising:
providing an array of unsingulated semiconductor packages, that are molded using a mold compound, the array having a bottom surface and a conductive terminal exposed to the bottom surface, the conductive terminal including a slot configured to receive solder material;
coupling a tape to the array;
applying a first saw blade to the bottom surface of the array to partially saw through a first thickness of the array between two individual, adjacent, unsingulated semiconductor packages, the first saw blade producing a kerf; and
applying a second saw blade into the kerf to fully saw through a remaining thickness of the array and produce a singulated semiconductor package, a width of the second saw blade narrower than a width of the first saw blade,
wherein the conductive terminal is exposed to a side surface of the singulated semiconductor package, and the first thickness is greater than the remaining thickness.