US 12,354,915 B2
Display substrate, manufacturing method thereof, and display apparatus
Liang Song, Beijing (CN); Long Jiang, Beijing (CN); Mingwen Wang, Beijing (CN); Pengyu Liao, Beijing (CN); Zhong Lu, Beijing (CN); Yuanjie Xu, Beijing (CN); Benlian Wang, Beijing (CN); Lili Du, Beijing (CN); and Donghua Jiang, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan Province (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 17/769,809
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan Province (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Apr. 29, 2021, PCT No. PCT/CN2021/090908
§ 371(c)(1), (2) Date Apr. 18, 2022,
PCT Pub. No. WO2022/226875, PCT Pub. Date Nov. 3, 2022.
Prior Publication US 2024/0153962 A1, May 9, 2024
Int. Cl. H10D 86/40 (2025.01); H01L 21/77 (2017.01); H10D 86/01 (2025.01); H10D 86/60 (2025.01)
CPC H01L 21/77 (2013.01) [H10D 86/0231 (2025.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base, having a wire routing region;
a first wire routing layer, located on the base, wherein the first wire routing layer in the wire routing region comprises a plurality of first routing wires arranged at intervals, and a space between adjacent first routing wires is smaller than 2 μm;
an insulation layer, located on a side of the first wire routing layer facing away from the base and having a plurality of first via holes corresponding to the first routing wires; and
a first flat layer, located on a side of the insulation layer facing away from the base and having second via holes corresponding to the first via holes, wherein the second via holes at least partially overlap with the first via holes;
wherein the insulation layer comprises a plurality of independent sub-insulation layers corresponding to the first routing wires, the sub-insulation layers have the first via holes, and a wire width of each of the first routing wires is smaller than or equal to 2 μm.