US 12,354,913 B2
Contact structure for semiconductor device
Yun-Yu Hsieh, Hsinchu (TW); Ying Ting Hsia, Kaohsiung (TW); Jeng Chang Her, Tainan (TW); Cha-Hsin Chao, Taipei (TW); Yi-Wei Chiu, Kaohsiung (TW); and Li-Te Hsu, Tainan County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,320.
Application 16/140,201 is a division of application No. 15/684,257, filed on Aug. 23, 2017, granted, now 10,083,863, issued on Sep. 25, 2018.
Application 18/362,320 is a continuation of application No. 17/397,621, filed on Aug. 9, 2021, granted, now 11,776,847.
Application 17/397,621 is a continuation of application No. 16/883,508, filed on May 26, 2020, granted, now 11,088,025, issued on Aug. 10, 2021.
Application 16/883,508 is a continuation of application No. 16/140,201, filed on Sep. 24, 2018, granted, now 10,679,896.
Claims priority of provisional application 62/512,323, filed on May 30, 2017.
Prior Publication US 2024/0021474 A1, Jan. 18, 2024
Int. Cl. H01L 21/768 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 23/485 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01)
CPC H01L 21/76895 (2013.01) [H01L 21/31116 (2013.01); H01L 21/32134 (2013.01); H01L 21/76805 (2013.01); H01L 21/76879 (2013.01); H01L 21/76886 (2013.01); H01L 21/76897 (2013.01); H01L 23/485 (2013.01); H10D 30/024 (2025.01); H10D 30/62 (2025.01); H10D 30/6219 (2025.01); H01L 21/76814 (2013.01); H01L 21/76831 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a transistor on a substrate, wherein the transistor comprises:
a fin structure on the substrate;
a source/drain (S/D) region over the fin structure; and
a gate structure adjacent to the S/D region;
forming a first dielectric layer over the fin structure;
forming an etch stop layer (ESL) on the first dielectric layer;
forming a second dielectric layer on the ESL;
forming a contact structure comprising a conductive material and in contact with the transistor, wherein the conductive material extends continuously through the first dielectric layer, the ESL, and the second dielectric layer; and
forming a concavely-curved surface on the contact structure.