US 12,354,908 B2
Amorphous layers for reducing copper diffusion and method forming same
Jyh-Nan Lin, Hsinchu (TW); Chia-Yu Wu, Hsinchu (TW); Kai-Shiung Hsu, Hsinchu (TW); and Ding-I Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 19, 2024, as Appl. No. 18/609,908.
Application 18/609,908 is a continuation of application No. 17/660,508, filed on Apr. 25, 2022, granted, now 11,967,522.
Application 17/660,508 is a continuation of application No. 16/890,413, filed on Jun. 2, 2020, granted, now 11,315,829, issued on Apr. 26, 2022.
Claims priority of provisional application 62/891,688, filed on Aug. 26, 2019.
Prior Publication US 2024/0258160 A1, Aug. 1, 2024
Int. Cl. H01L 21/768 (2006.01); C23F 1/12 (2006.01); H01L 21/02 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/76829 (2013.01) [C23F 1/12 (2013.01); H01L 21/02178 (2013.01); H01L 21/76802 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 23/53295 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure comprising:
a dielectric layer;
a first conductive feature in the dielectric layer;
a metal cap over and contacting the first conductive feature, wherein the metal cap is amorphous, and wherein at least a lower part of the metal cap is lower than a top surface of the dielectric layer;
a first etch stop layer over the metal cap, wherein the first etch stop layer has a first amorphous structure;
a second etch stop layer over the first etch stop layer, wherein the second etch stop layer has a second amorphous structure or a polycrystalline structure, and the second etch stop layer comprises a material different from a material of the first etch stop layer;
a low-k dielectric layer over the second etch stop layer; and
a second conductive feature in the low-k dielectric layer, the first etch stop layer, and the second etch stop layer.