US 12,354,904 B2
Method of reducing integrated deep trench optically sensitive defectivity
Abbas Ali, Plano, TX (US); and Scott Hiemke, McKinney, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Oct. 27, 2021, as Appl. No. 17/512,534.
Prior Publication US 2023/0126899 A1, Apr. 27, 2023
Int. Cl. H01L 21/74 (2006.01); H01L 21/762 (2006.01); H01L 23/58 (2006.01); H10D 1/00 (2025.01); H10D 1/66 (2025.01); H10D 1/68 (2025.01)
CPC H01L 21/74 (2013.01) [H01L 21/76224 (2013.01); H01L 23/585 (2013.01); H10D 1/692 (2025.01)] 27 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a deep trench in a semiconductor substrate, wherein the deep trench forms a continuous loop having linear sections and corner sections in the semiconductor substrate;
forming a sidewall dielectric layer in the deep trench;
filling the deep trench with a trench-fill material after forming the sidewall dielectric layer, the deep trench filled with the trench-fill material including a seam;
forming a patterned protective layer over the semiconductor substrate, the patterned protective layer covering the seam;
forming a shallow trench in the deep trench by removing the trench-fill material of the deep trench not covered by the patterned protective layer; and
forming a shallow trench isolation structure in the deep trench by filling the shallow trench with an oxide layer.