US 12,354,899 B2
Semiconductor devices and methods of manufacturing the same
Taeyong Kwon, Suwon-si (KR); Yoonjoong Kim, Suwon-si (KR); Youngjin Yang, Suwon-si (KR); and Dain Jang, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 11, 2023, as Appl. No. 18/133,242.
Claims priority of application No. 10-2022-0069415 (KR), filed on Jun. 8, 2022.
Prior Publication US 2023/0402307 A1, Dec. 14, 2023
Int. Cl. H01L 21/68 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/544 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H01L 21/68 (2013.01) [H01L 21/02381 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/76816 (2013.01); H01L 23/544 (2013.01); H10D 84/016 (2025.01); H10D 84/038 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate comprising a main chip region and a scribe lane region, wherein first trenches are formed in the scribe lane region;
a well region doped with impurities on an upper part of the main chip region;
align key patterns formed on surfaces of the first trenches and on surfaces of the substrate adjacent to the first trenches in the scribe lane region, wherein the align key patterns have an alternately and repeatedly stacked structure of a silicon germanium pattern and a silicon pattern; and
a multi-bridge channel transistor on the main chip region,
wherein at least one of the align key patterns comprises at least one second align key pattern in a partial region of the scribe lane region, and
wherein the at least one second align key pattern has a shape in which the stacked structure of a silicon germanium layer and a silicon layer is partially cut.