CPC H01L 21/32139 (2013.01) [H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/32136 (2013.01); H01L 21/76816 (2013.01); H01L 21/76832 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01)] | 20 Claims |
1. A method, comprising:
forming a first metal layer over a semiconductor substrate;
forming a second metal layer directly on the first metal layer, wherein a composition of the second metal layer is different from a composition of the first metal layer;
forming a metal-containing hard mask layer over the second metal layer;
patterning the metal-containing hard mask layer;
etching the second metal layer using the patterned metal-containing hard mask layer as an etch mask to form a conductive line, wherein the etched second metal layer exposes a portion of the first metal layer;
treating the exposed portion of the first metal layer with a plasma; and
removing both the patterned metal-containing hard mask layer and the treated exposed portion of the first metal layer in a wet etching process.
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