US 12,354,875 B2
Element forming wafer and method for manufacturing the same
Akihiko Teshigahara, Kariya (JP); and Megumi Suzuki, Kariya (JP)
Assigned to DENSO CORPORATION, Kariya (JP)
Filed by DENSO CORPORATION, Kariya (JP)
Filed on Apr. 29, 2022, as Appl. No. 17/732,688.
Application 17/732,688 is a continuation of application No. PCT/JP2020/042980, filed on Nov. 18, 2020.
Claims priority of application No. 2019-209854 (JP), filed on Nov. 20, 2019.
Prior Publication US 2022/0254637 A1, Aug. 11, 2022
Int. Cl. H01L 21/266 (2006.01); H01L 21/78 (2006.01); H10N 30/074 (2023.01); H10N 39/00 (2023.01)
CPC H01L 21/266 (2013.01) [H01L 21/78 (2013.01); H10N 30/074 (2023.02); H10N 39/00 (2023.02)] 2 Claims
OG exemplary drawing
 
1. An element forming wafer, comprising:
a semiconductor wafer having a plurality of chip forming regions; and
a thin layer formed on the semiconductor wafer, wherein
a plurality of portions of the thin layer each of which forms an element in each of the plurality of chip forming portions are defined as a plurality of element forming portions,
a plurality of regions are formed in the thin layer in one direction that passes through a center of the semiconductor wafer and that extends along an in-plane direction of the semiconductor wafer,
each of the plurality of element forming portions is arranged in a respective one of the plurality of regions,
a stress distribution that is along the one direction and is generated across the plurality of element forming portions has a maximum and a minimum of the stress in each of the plurality of regions, and
a rate of change in the stress between the maximum and the minimum in each of the plurality of regions is smaller than a rate of change in the stress at a boundary between adjacent ones of the plurality of regions.