US 12,354,870 B2
Multilayer stacking wafer bonding structure and method of manufacturing the same
Shou-Zen Chang, Hsinchu (TW); and Chun-Lin Lu, Hsinchu (TW)
Assigned to Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed by Powerchip Semiconductor Manufacturing Corporation, Hsinchu (TW)
Filed on Jan. 16, 2023, as Appl. No. 18/097,285.
Claims priority of application No. 111143326 (TW), filed on Nov. 14, 2022.
Prior Publication US 2024/0162035 A1, May 16, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H10D 48/32 (2025.01); H10D 89/00 (2025.01)
CPC H01L 21/02123 (2013.01) [H01L 21/02175 (2013.01); H01L 21/76816 (2013.01); H01L 24/05 (2013.01); H01L 24/29 (2013.01); H10D 48/366 (2025.01); H10D 89/217 (2025.01); H01L 2224/05085 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05181 (2013.01); H01L 2224/05184 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A multilayer stacking wafer bonding structure, comprising:
a logic wafer with a substrate and a logic circuit layer on said substrate;
multiple memory wafers stacked and bonded sequentially on said logic circuit layer of said logic wafer to constitute a first multilayer stacking structure, wherein each of said memory wafers comprises a memory layer, a silicon layer on said memory layer and multiple oxide layers in trenches of said silicon layer and connecting with said memory layer, and surfaces of said oxide layers and said silicon layer are flush, and said oxide layers in said memory wafers are aligned with each other in a direction vertical to said substrate;
multiple through-oxide vias (TOVs) extending through all of said memory layers and said oxide layers in said first multilayer stacking structure to said logic circuit layer of said logic wafer, and said TOVs do not extend through any of said silicon layers in said memory wafers; and
semiconductor via middle through-silicon vias (TSVs) in said logic wafer and connected with corresponding said TOVs.