US 12,354,706 B2
Control apparatus, memory, signal processing method, and electronic device
Jingwei Cheng, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 14, 2023, as Appl. No. 18/154,815.
Application 18/154,815 is a continuation of application No. PCT/CN2022/109916, filed on Aug. 3, 2022.
Claims priority of application No. 202210815505.8 (CN), filed on Jul. 8, 2022.
Prior Publication US 2024/0013825 A1, Jan. 11, 2024
Int. Cl. G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/106 (2013.01); G11C 7/1069 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A memory, comprising
a clock processing circuit and connected with a control apparatus,
wherein the memory is configured to, in a case where a first read instruction is received, determine a read data signal based on the first read instruction, determine a read clock signal through the clock processing circuit, and send the read data signal and the read clock signal together to the control apparatus; or,
in a case where a second read instruction is received, determine the read data signal based on the second read instruction, and send the read data signal to the control apparatus;
wherein the memory is further configured to control the read clock signal to be in a floating state in a case where the second read instruction is received.