US 12,354,704 B2
Active current consumption save mode for non-volatile memory using fast programming
Ke Zhang, Shanghai (CN); Linnan Chen, Shanghai (CN); Liang Li, Shanghai (CN); Minna Li, Shanghai (CN); Chin-Yi Chen, San Jose, CA (US); Xiaojia Jia, San Jose, CA (US); Muhammad Masuduzzaman, Chandler, AZ (US); and Xiang Yang, Santa Clara, CA (US)
Assigned to SANDISK TECHNOLOGIES, INC., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 24, 2023, as Appl. No. 18/225,491.
Claims priority of provisional application 63/449,106, filed on Mar. 1, 2023.
Prior Publication US 2024/0296877 A1, Sep. 5, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 8/08 (2006.01)
CPC G11C 7/1096 (2013.01) [G11C 7/1039 (2013.01); G11C 7/12 (2013.01); G11C 8/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in memory holes coupled to a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a controller coupled to the plurality of word lines and the memory holes and configured to:
successively apply each of a series of pulses of a program voltage to selected ones of the plurality of word lines while simultaneously applying one of a bit line program voltage and a bit line inhibit voltage to ones of the plurality of bit lines coupled to the memory holes containing groups of the memory cells connected to the selected ones of the plurality of word lines to program the groups of the memory cells with data during a program operation, the one of the bit line program voltage and the bit line inhibit voltage selected based on the data being programmed to the memory cells, and
maintain a voltage applied to ones of the plurality of bit lines as the bit line inhibit voltage in response to the ones of the plurality of bit lines remaining unselected when programming a next one of the groups of the memory cells.