US 12,354,703 B2
Memory device and ZQ calibration method
Kai Tian, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 2, 2023, as Appl. No. 18/364,026.
Application 18/364,026 is a continuation of application No. PCT/CN2022/123918, filed on Oct. 8, 2022.
Claims priority of application No. 202210716323.5 (CN), filed on Jun. 22, 2022.
Prior Publication US 2023/0420009 A1, Dec. 28, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 29/02 (2006.01)
CPC G11C 7/1063 (2013.01) [G11C 29/028 (2013.01); G11C 2207/2254 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a master chip and a plurality of slave chips, wherein the master chip and the plurality of slave chips are connected to a same calibration resistor;
the master chip and the plurality of slave chips are each provided with a first transmission terminal and a second transmission terminal, the first transmission terminal of the master chip and the first transmission terminals of the plurality of slave chips are connected to each other, and the second transmission terminal of the master chip and the second transmission terminals of the plurality of slave chips are connected to each other;
the first transmission terminals are configured to transmit a ZQ flag signal, and the second transmission terminals are configured to transmit an address signal; and
a first signal receiver and an address transmitter are provided in the master chip, and a second signal receiver is provided in each of the plurality of slave chip, wherein
the first signal receiver is configured to receive, by a ZQ signal terminal, a ZQ calibration command provided by a memory, the master chip starts calibration based on the ZQ calibration command, the master chip sends the ZQ flag signal through the first transmission terminal after completing the calibration, and the ZQ flag signal indicates that a current chip has completed calibration by using the calibration resistor;
the address transmitter sends the address signal through the second transmission terminal, and the address signal represents an address of a slave chip in the plurality of slave chip which will perform ZQ calibration;
the second signal receiver is configured to match the address signal and receive the ZQ flag signal through the first transmission terminal, a slave chip in the plurality of slave chip matching the address signal starts the calibration based on the ZQ flag signal, and a current slave chip in the plurality of slave chip sends the ZQ flag signal through the first transmission terminal after completing the calibration; and
the address transmitter continues to send a next address signal through the second transmission terminal, until the calibration of all of the plurality of slave chips is completed.