| CPC G11C 7/065 (2013.01) [G11C 7/08 (2013.01)] | 20 Claims |
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1. A circuit comprising:
first and second data lines;
a sense amplifier comprising first and second input terminals;
a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal;
a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal;
a third PMOS transistor coupled between the first data line and the first input terminal;
a fourth PMOS transistor coupled between the second data line and the second input terminal;
a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node; and
a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.
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