US 12,354,699 B2
Sensing amplifier circuit and memory device
Po-Yuan Tang, Hsinchu (TW); Chih-Chuan Ke, New Taipei (TW); Jian-Yuan Hsiao, Hsinchu (TW); and Yi-Ling Hung, Taoyuan (TW)
Assigned to VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by Vanguard International Semiconductor Corporation, Hsinchu (TW)
Filed on Nov. 2, 2023, as Appl. No. 18/500,394.
Prior Publication US 2025/0149071 A1, May 8, 2025
Int. Cl. G11C 7/06 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01)
CPC G11C 7/06 (2013.01) [G11C 17/16 (2013.01); G11C 17/18 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A sensing amplifier circuit coupled to a memory cell through a data line, comprising:
a first P-type transistor comprising a gate coupled to the data line at an input node, a source and a bulk coupled to a first node, and a drain coupled to an output node;
a second P-type transistor comprising a gate coupled to an inverted reading-triggered signal, a source coupled to a voltage source, and a drain coupled to the first node;
a first N-type transistor comprising a gate coupled to the input node, a drain coupled to the output node, and a source coupled to a ground; and
a second N-type transistor comprising a gate receiving the inverted reading-triggered signal, a drain coupled to the output node, and a source coupled to the ground,
wherein the first P-type transistor further comprises an N-type well region, and the source and bulk of the first P-type transistor are electrically connected to the N-type well region.