US 12,354,680 B2
High performance verify techniques in a memory device
Xiang Yang, Santa Clara, CA (US); Wei Cao, Fremont, CA (US); and Deepanshu Dutta, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Sep. 30, 2022, as Appl. No. 17/957,606.
Prior Publication US 2024/0112744 A1, Apr. 4, 2024
Int. Cl. G11C 11/34 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of programming a memory device, comprising the steps of:
receiving a command to write user data to the memory device;
preparing at least one memory block that includes a plurality of memory cells arranged in a plurality of word lines;
on at least a portion of a selected word line of the plurality of word lines, performing a smart verify operation to acquire a smart verify programming voltage; and
after the smart verify programming voltage is acquired, in a plurality of program loops, programming the memory cells of the selected word line to include the user data and data that corresponds to the smart verify programming voltage.