US 12,354,679 B2
Memory system for performing an erase voltage application operation and an erase verify operation for a nonvolatile memory
Takumi Fujimori, Yamato (JP); Tetsuya Sunata, Yokohama (JP); Masanobu Shirakawa, Chigasaki (JP); and Hidehiro Shiga, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 7, 2023, as Appl. No. 18/179,505.
Claims priority of application No. 2022-092347 (JP), filed on Jun. 7, 2022.
Prior Publication US 2023/0395167 A1, Dec. 7, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/16 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory system comprising:
a nonvolatile memory including a plurality of blocks each including a plurality of memory cells and being a unit of erasure; and
circuitry programmed to transmit a first command set for an erase voltage application operation and a second command set for an erase verify operation to the nonvolatile memory, to erase data in at least one of the blocks,
wherein the circuitry is programmed to:
select a first block targeted for erasure from the plurality of blocks;
make a comparison between a first erase voltage application accumulated time period and a first erase verify permission time period each corresponding to the first block;
transmit the first command set to the nonvolatile memory to execute the erase voltage application operation in a case where the first erase voltage application accumulated time period is less than the first erase verify permission time period; and
transmit the second command set to the nonvolatile memory to execute the erase verify operation in a case where the first erase voltage application accumulated time period is equal to or greater than the first erase verify permission time period, and
the nonvolatile memory is programmed to execute the erase voltage application operation based on the first command set and to execute the erase verify operation based on the second command set.