US 12,354,678 B2
Non-volatile memory with efficient testing
Jayavel Pachamuthu, San Jose, CA (US); Dana Lee, Saratoga, CA (US); and Jiahui Yuan, Fremont, CA (US)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed on Apr. 26, 2022, as Appl. No. 17/729,331.
Application 17/729,331 is a continuation in part of application No. 17/403,052, filed on Aug. 16, 2021, granted, now 11,657,884.
Prior Publication US 2023/0058836 A1, Feb. 23, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a non-volatile memory structure comprising a plurality of blocks of memory cells and a plurality of word lines, the plurality of word lines including even word lines and odd word lines, the memory cells are arranged in groups; and
a control circuit connected to the non-volatile memory structure, the control circuit is configured to program data to a first block of the plurality of blocks after erasing the first block if erasing the first block was successful;
the control circuit is configured to determine whether the erasing the first block was successful prior to the first block having experienced a failed read process by testing whether the first block has erase verified successfully;
the control circuit is configured to determine whether the erasing the first block was successful after the first block experienced a failed read process by testing whether the first block has erase verified successfully and additionally by testing whether a number of groups having memory cells connected to even word lines in the first block that have a different erase verify result than memory cells connected to odd word lines in the first block is greater than a defect test threshold.