US 12,354,677 B2
Semiconductor storage device
Hiroki Date, Chigasaki Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 20, 2023, as Appl. No. 18/337,589.
Claims priority of application No. 2022-149513 (JP), filed on Sep. 20, 2022.
Prior Publication US 2024/0096430 A1, Mar. 21, 2024
Int. Cl. G11C 16/30 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3436 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor storage device comprising:
a plurality of memory cell transistors;
a word line electrically connected in common to respective gates of the plurality of memory cell transistors;
a voltage generator configured to generate a first voltage transferred to the word line, the voltage generator including:
a charge pump circuit;
a voltage divider configured to divide the first voltage with a first resistance element and a second resistance element, at least any of the first resistance element and the second resistance element being a variable resistance element that receives a first digital signal indicating a resistance value and is changeable to the resistance value; and
a detector including a first input terminal connected to the voltage divider and a second input terminal different from the first input terminal, and configured to detect a monitor voltage supplied to the first input terminal based on a reference voltage supplied to the second input terminal, and control the charge pump circuit; and
a control unit configured to output the first digital signal,
wherein the control unit outputs the first digital signal such that a theoretical waveform of the first voltage in boosting the first voltage in an erasing verifying operation is different from a theoretical waveform of the first voltage in boosting the first voltage in a reading operation.