US 12,354,675 B2
Nonvolatile memory device including power gating circuit and input/output circuit of a nonvolatile memory device
Hojun Yoon, Suwon-si (KR); Jinha Hwang, Suwon-si (KR); Seunghoon Lee, Suwon-si (KR); Youngchul Cho, Suwon-si (KR); Youngdon Choi, Suwon-si (KR); and Junghwan Choi, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jan. 23, 2023, as Appl. No. 18/100,173.
Claims priority of application No. 10-2022-0073472 (KR), filed on Jun. 16, 2022.
Prior Publication US 2023/0410917 A1, Dec. 21, 2023
Int. Cl. G11C 11/34 (2006.01); G11C 16/24 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 16/24 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An input/output circuit of a nonvolatile memory device, comprising:
a driver connected to a data line and configured to output data from a memory cell of the nonvolatile memory device to the data line; and
a power gating circuit connected between the driver and a power terminal or between the driver and a ground terminal and configured to block a leakage current of the driver,
wherein the power gating circuit includes a plurality of transistors electrically connected in parallel and having threshold voltages of different magnitudes, respectively, and
wherein the driver includes a plurality of transistors each connected to the data line and configured to be turned on based on a signal corresponding to the data.