US 12,354,674 B2
Non-volatile memory power cycle protection mechanism
John J. Sullivan, Sunnyvale, CA (US); James M. Hollabaugh, San Jose, CA (US); Jason W. Brinsfield, San Francisco, CA (US); Calvin M. Ryan, Berkeley, CA (US); and Andreas Adler, Schlierbach (DE)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 26, 2022, as Appl. No. 17/874,100.
Prior Publication US 2024/0038310 A1, Feb. 1, 2024
Int. Cl. G11C 16/30 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 16/102 (2013.01); G11C 16/14 (2013.01); G11C 16/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a memory circuit comprising non-volatile flash memory;
a power rail providing power to the non-volatile flash memory; and
a power management circuit coupled to the memory circuit and the power rail, wherein the power management circuit regulates power provided from the power rail to the non-volatile flash memory, wherein the power management circuit is configured to receive a power reset signal, and wherein, in response to receiving the power reset signal at the power management circuit, the power management circuit is configured to:
receive an activity output signal from a portion of the non-volatile flash memory dedicated to output a binary value in the activity output signal corresponding to whether the portion is active or inactive;
assess the binary value in the activity output signal, the binary value indicating whether the portion is active or inactive at a time the power reset signal is received at the power management circuit;
reset the power on the power rail provided to the non-volatile flash memory when the binary value indicates the portion is inactive at the time the power reset signal is received at the power management circuit; and
inhibit resetting the power on the power rail provided to the non-volatile flash memory when the binary value indicates the portion is active at the time the power reset signal is received at the power management circuit.