US 12,354,673 B2
Latch type sense amplifier for non-volatile memory
Hsin-Chan Peng, Hsinchu County (TW)
Assigned to EMEMORY TECHNOLOGY INC., Hsin-Chu (TW)
Filed by eMemory Technology Inc., Hsin-Chu (TW)
Filed on Nov. 7, 2023, as Appl. No. 18/387,476.
Claims priority of provisional application 63/424,966, filed on Nov. 14, 2022.
Prior Publication US 2024/0161811 A1, May 16, 2024
Int. Cl. G11C 7/06 (2006.01); G11C 13/00 (2006.01); G11C 16/26 (2006.01); G11C 16/28 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 7/065 (2013.01); G11C 13/004 (2013.01); G11C 16/28 (2013.01); G11C 2013/0042 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A latch type sense amplifier for a non-volatile memory, a selected memory cell of the non-volatile memory being connected with a data line, the latch type sense amplifier comprising:
a first transistor, wherein a first drain/source terminal of the first transistor is connected with a first node, a second drain/source terminal of the first transistor is connected with a second node, a gate terminal of the first transistor receives a reference voltage, and the gate terminal of the first transistor is a first input terminal of the latch type sense amplifier;
a second transistor, wherein a first drain/source terminal of the second transistor is connected with the first node, a second drain/source terminal of the second transistor is connected with a third node, a gate terminal of the second transistor is connected with the data line, and the gate terminal of the second transistor is a second input terminal of the latch type sense amplifier
a third transistor, wherein a first drain/source terminal of the third transistor receives a first supply voltage, a second drain/source terminal of the third transistor is connected with the first node, and a gate terminal of the third transistor receives an enable signal;
a latching device connected with the second node and the third node;
a first capacitor, wherein a first terminal of the first capacitor is connected with the gate terminal of the third transistor, and a second terminal of the first capacitor is connected with the gate terminal of the first transistor; and
a second capacitor, wherein a first terminal of the second capacitor is connected with the gate terminal of the third transistor, and a second terminal of the second capacitor is connected with the gate terminal of the second transistor.