US 12,354,671 B2
Semiconductor memory device
Koji Kato, Yokohama (JP); Yuki Shimizu, Yokohama (JP); and Shuhei Oketa, Yokohama (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Mar. 16, 2023, as Appl. No. 18/184,893.
Claims priority of application No. 2022-074383 (JP), filed on Apr. 28, 2022.
Prior Publication US 2023/0352099 A1, Nov. 2, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 5/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/32 (2006.01); H01L 23/528 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 5/06 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/30 (2013.01); G11C 16/32 (2013.01); H01L 23/5283 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of first conductive layers arranged in a first direction, extending in a second direction intersecting with the first direction, and overlapping with a sense amplifier region viewed from the first direction;
a plurality of second conductive layers arranged in the first direction, extending in the second direction, and not overlapping with the sense amplifier region viewed from the first direction;
a first semiconductor layer extending in the first direction and opposed to the first conductive layers;
a second semiconductor layer extending in the first direction and opposed to the second conductive layers;
a first electric charge accumulating portion disposed between the first conductive layers and the first semiconductor layer;
a second electric charge accumulating portion disposed between the second conductive layers and the second semiconductor layer;
a first bit line electrically connected to one end of the first semiconductor layer;
a second bit line electrically connected to one end of the second semiconductor layer;
a first driver circuit that controls a voltage applied to one of the first conductive layers; and
a second driver circuit that controls a voltage applied to one of the second conductive layers, wherein
at least a part of first operation parameters including magnitudes and supply times of a plurality of voltages applied to the one of the first conductive layers when a predetermined operation is performed on a first memory cell including the first electric charge accumulating portion, the at least a part of first operation parameters differing from
at least a part of second operation parameters including magnitudes and supply times of a plurality of voltages applied to the one of the second conductive layers when the predetermined operation is performed on a second memory cell including the second electric charge accumulating portion.