US 12,354,664 B2
Non-volatile memory with loop dependant ramp-up rate
Abu Naser Zainuddin, Milpitas, CA (US); Jiahui Yuan, Fremont, CA (US); and Toru Miwa, Yokohama (JP)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Jul. 24, 2023, as Appl. No. 18/357,339.
Claims priority of provisional application 63/479,409, filed on Jan. 11, 2023.
Prior Publication US 2024/0233826 A1, Jul. 11, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile storage apparatus, comprising:
a plurality of non-volatile memory cells;
a plurality of word lines connected to the memory cells; and
a control circuit connected to the memory cells and word lines, the control circuit is configured to program the memory cells by applying doses of programming to the memory cells and performing program-verify between doses of programming, the control circuit is configured to perform program-verify between doses of programming by applying a verify reference voltage to a selected word line and applying an overdrive voltage to unselected word lines between the doses of programming, the control circuit is configured to apply the overdrive voltage to unselected word lines at a first ramp-up rate between a first set of the doses of programming and at a second ramp-up rate between a second set of the doses of programming, the second ramp-up rate is lower than the first ramp-up rate.