US 12,354,640 B2
Memory device refresh operations
Dongha Kim, Suwon-si (KR); Hyunki Kim, Suwon-si (KR); Sungchul Park, Suwon-si (KR); Ju-Seop Park, Suwon-si (KR); and Dongsu Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 17, 2023, as Appl. No. 18/171,121.
Claims priority of application No. 10-2022-0094036 (KR), filed on Jul. 28, 2022.
Prior Publication US 2024/0038288 A1, Feb. 1, 2024
Int. Cl. G11C 11/406 (2006.01)
CPC G11C 11/40622 (2013.01) [G11C 11/40603 (2013.01); G11C 11/40611 (2013.01); G11C 11/40615 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array comprising a plurality of rows;
a queue; and
a control circuit configured to:
at a random time, determine an aggressor row address, the aggressor row address indicating an aggressor row among the plurality of rows;
store the aggressor row address or a value derived from the aggressor row address in the queue; and
in response to a first targeted refresh command, control a refresh operation of one or more victim rows of the plurality of rows based on the aggressor row address.