| CPC G11C 11/406 (2013.01) | 20 Claims |
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1. A memory device, comprising:
a memory cell array including a plurality of memory cell rows;
a row hammer managing circuit configured to:
detect an earlier row hammer address during an earlier monitoring period,
detect a row hammer address by comparing the earlier row hammer address to each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to the plurality of memory cell rows, and
output the row hammer address in response to a refresh command provided from a host; and
a refresh control circuit configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address; and
wherein the earlier monitoring period precedes, in time, the monitoring period for monitoring the plurality of access to the plurality of memory cell rows.
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