US 12,354,633 B2
Spacer film scheme form polarization improvement
Tzu-Yu Lin, Taoyuan (TW); and Yao-Wen Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manfacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 3, 2024, as Appl. No. 18/763,154.
Application 18/763,154 is a continuation of application No. 18/150,281, filed on Jan. 5, 2023, granted, now 12,119,035.
Claims priority of provisional application 63/412,969, filed on Oct. 4, 2022.
Claims priority of provisional application 63/393,347, filed on Jul. 29, 2022.
Prior Publication US 2024/0355358 A1, Oct. 24, 2024
Int. Cl. G11B 9/02 (2006.01); H10B 51/30 (2023.01)
CPC G11B 9/02 (2013.01) [H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a lower electrode;
a high-k material structure disposed over the lower electrode;
an upper electrode disposed over a central region of the high-k material structure; and
a stressed dielectric spacer arranged on a peripheral region of the high-k material structure, wherein the high-k material structure has an orthorhombic phase concentration that varies between the central region and the peripheral region.