US 12,354,559 B2
Shift register, gate drive circuit and display device
Xuehuan Feng, Beijing (CN); and Yongqian Li, Beijing (CN)
Assigned to Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/685,922
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Oct. 31, 2022, PCT No. PCT/CN2022/128664
§ 371(c)(1), (2) Date Feb. 23, 2024,
PCT Pub. No. WO2024/092416, PCT Pub. Date May 10, 2024.
Prior Publication US 2025/0182698 A1, Jun. 5, 2025
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3258 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3258 (2013.01); G09G 2300/0804 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0626 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A shift register comprising:
a voltage regulating module that is connected with a preceding stage light emitting cascade signal output terminal, a first clock signal terminal, a second clock signal terminal, a first power supply terminal, a second power supply terminal, a first node and a second node, wherein the voltage regulating module is configured to adjust voltages at the first node and the second node in response to control of signals provided by the preceding stage light emitting cascade signal output terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal and the second power supply terminal;
a light emitting cascade output module that is connected with the first power supply terminal, the second power supply terminal, a light emitting cascade signal output terminal, the first node, and the second node, wherein the light emitting cascade output module is configured to supply a first voltage of the first power supply terminal or a second voltage of the second power supply terminal to the light emitting cascade signal output terminal in response to control of the voltage at the first node and in response to control of the voltage at the second node;
a node control module that is connected with the first node, a subsequent stage gate cascade signal output terminal, the second power supply terminal, a third node, and the second clock signal terminal, wherein the node control module is configured to adjust a voltage at the third node in response to control of signals provided by the subsequent stage gate cascade signal output terminal, the first node, and the second clock signal terminal; and
a light emitting drive output module that is connected to the second node and connected to the third node, the first power supply terminal, the second power supply terminal, and a light emitting control drive signal output terminal, wherein the light emitting drive output module is configured to supply the first voltage of the first power supply terminal to a light emitting control drive signal output terminal in response to control of the voltage at the third node, to supply the second voltage of the second power supply terminal to the light emitting control drive signal output terminal in response to the control of the voltage at the second node, and to supply the second voltage of the second power supply terminal to the light emitting control drive signal output terminal in response to the control of the voltage at the second node;
or, a light emitting drive output module that is connected with the second node, the third node, the first power supply terminal, the second power supply terminal, the subsequent stage gate cascade signal output terminal and the light emitting control drive signal output terminal, wherein the light emitting drive output module is configured to supply the first voltage of the first power supply terminal to the light emitting control drive signal output terminal in response to control of the voltage at the third node, and to supply the second voltage of the second power supply terminal to the light emitting control drive signal output terminal in response to the control of the voltage at the second node and control of the subsequent stage gate cascade signal output terminal.