US 12,354,558 B2
Driving circuit, driving method, driving module and display device
Ziyang Yu, Beijing (CN); Haijun Qiu, Beijing (CN); Ming Hu, Beijing (CN); Zhiliang Jiang, Beijing (CN); Tianyi Cheng, Beijing (CN); Jianpeng Wu, Beijing (CN); Wenbo Chen, Beijing (CN); Mengqi Wang, Beijing (CN); Cong Liu, Beijing (CN); Qian Xu, Beijing (CN); Qingqing Yan, Beijing (CN); Pan Zhao, Beijing (CN); Qing He, Beijing (CN); Xiangnan Pan, Beijing (CN); and Quanyong Gu, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 18/558,383
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Dec. 19, 2022, PCT No. PCT/CN2022/140042
§ 371(c)(1), (2) Date Nov. 1, 2023,
PCT Pub. No. WO2024/130490, PCT Pub. Date Jun. 27, 2024.
Prior Publication US 2025/0087166 A1, Mar. 13, 2025
Int. Cl. G09G 3/3266 (2016.01); G09G 3/3258 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/3258 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A driving circuit, comprising a driving signal generation circuit, a gating circuit, an output control circuit and an output circuit; wherein
the driving signal generation circuit is configured to generate and output an Nth stage of driving signal through an Nth stage of driving signal output terminal;
the gating circuit is electrically connected to a first node, a gating input terminal and a gating control terminal respectively, and is configured to control to write a gating input signal provided by the gating input terminal into the first node under the control of a gating control signal provided by the gating control terminal;
a first terminal of the output control circuit is electrically connected to the Nth stage of driving signal output terminal, and a second terminal of the output control circuit is electrically connected to the first node, the output control circuit is configured to perform a NAND operation on the Nth stage of driving signal and a potential of the second terminal of the output control circuit to obtain a first output signal;
the output circuit is configured to invert the first output signal to obtain and provide an output driving signal through an output driving terminal;
N is a positive integer.