US 12,354,538 B2
Array substrate and driving method therefor, and display apparatus
Xiuling Li, Beijing (CN); Qibing Gu, Beijing (CN); Guofeng Hu, Beijing (CN); Hongge Mei, Beijing (CN); Nana Gao, Beijing (CN); Bao Fu, Beijing (CN); Xiangyi Chen, Beijing (CN); Lingyun Shi, Beijing (CN); and Wenchieh Huang, Beijing (CN)
Assigned to BOE MLED Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by BOE MLED Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Jun. 27, 2024, as Appl. No. 18/756,624.
Application 18/756,624 is a continuation of application No. 18/044,664, previously published as PCT/CN2021/070955, filed on Jan. 8, 2021.
Prior Publication US 2024/0346995 A1, Oct. 17, 2024
Int. Cl. G09G 3/32 (2016.01); G09G 3/20 (2006.01)
CPC G09G 3/32 (2013.01) [G09G 2300/0452 (2013.01); G09G 2310/0202 (2013.01); G09G 2310/08 (2013.01)] 11 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a base substrate;
a plurality of pixels located on the base substrate; wherein the plurality of the pixels are arranged in an array in a first direction and a second direction, and the first direction and the second direction intersect each other; at least one pixel of the plurality of the pixels comprises sub-pixels, and a pixel driving chip for driving each of the sub-pixels in the pixel; wherein a sub-pixel of the sub-pixels comprises at least one light emitting diode; and the pixel driving chip comprises a data signal end and an addressing signal end;
a plurality of addressing signal lines located on the base substrate; wherein an addressing signal line of the addressing signal lines is coupled to addressing signal ends of pixel driving chips of a row of the pixels arranged in the first direction, and the addressing signal ends of the pixel driving chips of the row of the pixels arranged in the first direction are connected in parallel through the addressing signal line; and
a plurality of data lines located on the base substrate; wherein a data line of the data lines is coupled to data signal ends of pixel driving chips of a column of the pixels arranged in the second direction, and the data signal ends of the pixel driving chips of the column of the pixels arranged in the second direction are connected in parallel through the data line;
wherein each of the pixel driving chips is configured to drive one of the pixels;
wherein the array substrate further comprises a plurality of fixed voltage signal lines;
the pixel driving chip further comprises a fixed voltage signal end;
the fixed voltage signal lines are coupled to fixed voltage signal ends of the pixel driving chips of a column of the pixels arranged in the second direction;
the array substrate further comprises a plurality of auxiliary signal lines;
the auxiliary signal lines extend in the first direction and are arranged in the second direction;
an auxiliary signal line of the auxiliary signal lines is located in a gap between two adjacent rows of the pixels arranged in the first direction; and
the auxiliary signal lines and the fixed voltage signal lines are arranged in different layers, and each auxiliary signal line is coupled to at least one fixed voltage signal line through a second via hole; and the second via hole penetrates an insulating layer between the auxiliary signal line and the fixed voltage signal line;
the second via hole is formed in an area where there is overlap between orthogonal projections of the fixed voltage signal line and the auxiliary signal line on the base substrate.
 
7. A driving method for the array substrate according to claim 1, comprising:
each display frame comprising at least: an address assignment phase and a data signal transfer phase;
sequentially inputting addressing information into each addressing signal line in the address assignment phase; wherein the addressing information comprises address information corresponding to a row of pixels arranged in a first direction; and
separately inputting data information to each data line in the data signal transfer phase; wherein the data information comprises a plurality of pieces of sub-data information; and each piece of sub-data information comprises address information corresponding to each pixel, and pixel data information, corresponding to the address information, of the pixel coupled to the data line.