| CPC G09G 3/32 (2013.01) [G09G 3/3426 (2013.01); G09G 2300/0814 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0257 (2013.01); G09G 2320/0633 (2013.01); G09G 2320/064 (2013.01); G09G 2320/066 (2013.01)] | 19 Claims |

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1. An integrated circuit comprising:
a first pin configured to receive an image signal;
a second pin configured to receive a scan signal;
a driver transistor configured to generate an output current according to a voltage of a gate node based on the scan signal and the image signal; and
an overvoltage detection circuit configured to generate a detection signal in response to a voltage of an output pin exceeding a reference voltage, and
the overvoltage detection circuit including an off transistor configured to block the output current by discharging the gate node based on the detection signal.
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