| CPC G09G 3/32 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2300/0861 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01); G09G 2340/0435 (2013.01)] | 21 Claims |

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1. A display panel comprising:
a first display region to an N-th display region disposed in a row direction, wherein N is an integer of 2 or greater,
wherein a P-th display region, where P is an integer between 1 and N, includes:
a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor which receives an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, where the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal; and
a P-th region control circuit which outputs the compensation gate signal to the first pixel compensation transistor, wherein the P-th region control circuit includes a first control transistor which outputs a high gate voltage of the compensation gate signal, and a second control transistor which outputs a low gate voltage of the compensation gate signal, wherein the first control transistor and the second control transistor are controlled based on a P-th region control signal.
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