US 12,354,522 B2
Source buffer output switch control circuit and method of driving the same
Eunkyu Seong, Cheongju-si (KR); and Hyoungkyu Kim, Cheongju-si (KR)
Assigned to Magnachip Mixed-Signal, Ltd., Cheongju-si (KR)
Filed by Magnachip Mixed-Signal, Ltd., Cheongju-si (KR)
Filed on Sep. 11, 2023, as Appl. No. 18/464,418.
Claims priority of application No. 10-2023-0028441 (KR), filed on Mar. 3, 2023.
Prior Publication US 2024/0296776 A1, Sep. 5, 2024
Int. Cl. G09G 3/20 (2006.01); H03K 17/0812 (2006.01)
CPC G09G 3/2092 (2013.01) [H03K 17/08122 (2013.01); G09G 2310/0291 (2013.01); G09G 2330/06 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A source buffer output switch control circuit for controlling operations of a source buffer output switch configured to transmit a source signal output from a source buffer to a display panel or block the source signal, the source buffer output switch control circuit comprising:
a switch driver configured to generate a switch control signal for controlling the operations of the source buffer output switch based on a switch operation input signal;
a current limiter configured to limit a driving current applied to the switch driver in order to control a slew rate of the switch control signal; and
a bias block configured to generate a bias voltage based on a value of a two-bit input parameter input to the bias block and to transmit the bias voltage to the current limiter to control a magnitude of the driving current,
wherein as the value of the two-bit input parameter input to the bias block increases from ‘00’ to ‘01’, ‘10’, and ‘11’, the bias block is configured to transmit a higher first bias voltage to a gate of a PMOS transistor of the current limiter and a lower second bias voltage to a gate of an NMOS transistor of the current limiter than when the value is “00” to increase a slewing time of the switch control signal.