| CPC G09G 3/20 (2013.01) [G09G 2300/0413 (2013.01); G09G 2330/02 (2013.01)] | 16 Claims |
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1. A driving circuit, comprising an input circuit, an output circuit, a first pull-down node, a first control circuit and a pull-up node reset circuit; wherein
the first control circuit is electrically connected to the first pull-down node, a first control terminal, and a first voltage terminal, respectively, is configured to control to connect the first pull-down node and the first voltage terminal under the control of a first control signal provided by the first control terminal, so that a potential of the first pull-down node is a valid voltage;
the pull-up node reset circuit is electrically connected to the first pull-down node, a pull-up node, and a second voltage terminal, and is configured to control to connect the pull-up node and the second voltage terminal when the potential of the first pull-down node is the valid voltage, so as to reset a potential of the pull-up node;
wherein the first control terminal is a reset terminal; wherein the reset terminal refers to: when a plurality of stages of driving circuits cascaded to each other are comprised, a current stage of driving circuit is a nth stage of driving circuit, for forward scanning, the reset terminal is connected to an output terminal of a (n+i)th stage of driving circuit, wherein n is a positive integer greater than or equal to 1, i is a positive integer greater than or equal to 1; or, for the driving circuit in which a cascaded output terminal and a gate scanning output terminal are separately output, the reset terminal is a signal terminal connected to the cascaded output terminal;
the driving circuit further comprises a first pull-down node control circuit; wherein
the first pull-down node control circuit is electrically connected to the first pull-down node, a first pull-down control node, the pull-up node, a first control voltage terminal and a third voltage terminal, is configured to control to connect the first control voltage terminal and the first pull-down control node under the control of the first control voltage provided by the first control voltage terminal, and control to connect the first pull-down control node and the third voltage terminal under the control of the potential of the pull-up node, and control to connect the first pull-down control node and the first control voltage terminal under the control of the potential of the first pull-down control node, and control to connect the first pull-down node and the third voltage terminal under the control of the potential of the pull-up node; and the third voltage terminal is a low voltage terminal;
the first voltage terminal is the first control voltage terminal;
the input circuit is respectively electrically connected to an input terminal, a second input voltage terminal and the pull-up node, and is configured to control to write a second input voltage provided by the second input voltage terminal into the pull-up node under the control of an input signal provided by the input terminal;
wherein the output circuit is electrically connected to the pull-up node, the first pull-down node, an output clock signal terminal, a fourth voltage terminal and a driving signal output terminal, and is configured to control to write an output clock signal provided by the output clock signal terminal into the driving signal output terminal under the control of the potential of the pull-up node, and control to connect the driving signal output terminal and the fourth voltage terminal under the control of the potential of the first pull-down node;
wherein the driving circuit further comprises an output reset circuit; the output reset circuit is electrically connected to a frame reset terminal, the driving signal output terminal and the fourth voltage terminal respectively, and is configured to control to connect the driving signal output terminal and the fourth voltage terminal under the control of a frame reset signal provided by the frame reset terminal; the output reset circuit comprises a seventeenth transistor; a gate electrode of the seventeenth transistor is electrically connected to the frame reset terminal, a first electrode of the seventeenth transistor is electrically connected to the driving signal output terminal, and a second electrode of the seventeenth transistor is electrically connected to the fourth voltage terminal;
wherein the driving circuit further comprises an initial reset circuit; the initial reset circuit comprises an eighteenth transistor; a gate electrode of the eighteenth transistor is electrically connected to an initial reset terminal, a first electrode of the eighteenth transistor is electrically connected to the pull-up node, and a second electrode of the eighteenth transistor is electrically connected to the fourth voltage terminal; and the initial reset circuit is configured to reset the potential of the pull-up node at a front frame;
wherein the driving circuit further comprises a reset circuit, the reset circuit comprises a fifth transistor; a gate electrode of the fifth transistor is electrically connected to the reset terminal, a first electrode of the fifth transistor is electrically connected to the pull-up node, and a second electrode of the fifth transistor is electrically connected to a first input voltage terminal; and
wherein a signal phase of a first control voltage provided by first control voltage terminal is opposite to a signal phase of a frame reset signal provided by the frame reset terminal.
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