US 12,353,982 B2
Convolution block array for implementing neural network application and method using the same, and convolution block circuit
Woon-Sik Suh, New Taipei (CN)
Appl. No. 17/291,309
Filed by GENESYS LOGIC, INC., New Taipei (CN)
PCT Filed Apr. 30, 2019, PCT No. PCT/CN2019/085197
§ 371(c)(1), (2) Date May 5, 2021,
PCT Pub. No. WO2020/093669, PCT Pub. Date May 14, 2020.
Claims priority of provisional application 62/756,095, filed on Nov. 6, 2018.
Prior Publication US 2022/0027714 A1, Jan. 27, 2022
Int. Cl. G06N 3/063 (2023.01); G06F 1/03 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 7/53 (2006.01); G06F 7/544 (2006.01); G06F 9/54 (2006.01); G06N 3/048 (2023.01); G06N 3/08 (2023.01)
CPC G06N 3/063 (2013.01) [G06F 1/03 (2013.01); G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/53 (2013.01); G06F 7/5443 (2013.01); G06F 9/54 (2013.01); G06N 3/048 (2023.01); G06N 3/08 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A convolution block array for implementing a neural network application, comprising:
a plurality of convolution block circuits configured to process a convolution operation of the neural network application, wherein each of the convolution block circuits comprising:
a plurality of multiplier circuits configured to perform the convolution operation; and
at least one adder circuit connected to the plurality of multiplier circuits and configured to perform an adding operation of results of the convolution operation and generate an output signal;
wherein at least one of the convolution block circuits comprises at least an idle multiplier circuit and a convolution operation multiplier circuit and the one of the convolution block circuits is configured to concurrently perform a biasing operation and the convolution operation of the neural network application, such that the idle multiplier circuit performs the biasing operation and the convolution operation multiplier circuit performs the convolution operation, wherein a biasing coefficient passes to the at least one adder circuit through the idle multiplier circuit of the plurality of multiplier circuits, and the convolution operation is executed by multiplying feature values by weight coefficients and adding the biasing coefficient.