US 12,353,928 B2
Method for an internal command from a plurality of processing cores with memory sub-system that cache identifiers for access commands
John Traver, Boise, ID (US); and Jay R. Shoen, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 23, 2024, as Appl. No. 18/643,656.
Application 18/643,656 is a continuation of application No. 17/945,673, filed on Sep. 15, 2022, granted, now 11,989,600.
Application 17/945,673 is a continuation of application No. 16/841,935, filed on Apr. 7, 2020, granted, now 11,474,885, issued on Oct. 18, 2022.
Prior Publication US 2024/0272967 A1, Aug. 15, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/00 (2018.01); G06F 9/38 (2018.01); G06F 9/54 (2006.01); G06F 12/02 (2006.01); G06F 12/084 (2016.01); G06F 12/0871 (2016.01)
CPC G06F 9/544 (2013.01) [G06F 9/3836 (2013.01); G06F 9/546 (2013.01); G06F 12/0246 (2013.01); G06F 12/084 (2013.01); G06F 12/0871 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
processing circuitry associated with one or more memory devices and configured to cause the apparatus to:
receive an access command to perform an access operation on a transfer unit of a memory sub-system, wherein the transfer unit is associated with one or more logical blocks;
store an identifier associated with an internal command in a shared memory that is accessible by a plurality of cores of the memory sub-system based at least in part on receiving the access command;
determine whether the access operation was completed based at least in part on storing the identifier; and
update the internal command based at least in part on determining that the access operation was not completed.