| CPC G06F 9/5016 (2013.01) [G06F 9/5022 (2013.01); G06F 9/5033 (2013.01); G06F 9/5038 (2013.01); G06F 13/1621 (2013.01); G06F 13/1689 (2013.01)] | 18 Claims |
|
1. An apparatus, comprising:
control circuitry;
memory controller circuitry configured to satisfy different quality-of-service parameters for multiple different classes of request traffic that access a memory;
multiple agents configured to send requests to the memory controller circuitry, wherein:
the control circuitry is configured to impose a rate limit for a first class of traffic utilized by an agent of the multiple agents and provide a latency quality-of-service guarantee for the first class of traffic; and
the memory controller circuitry is configured to process at least the following types of operations in the first class of traffic: read requests and write requests; and
cache circuitry configured to cache data from the memory;
wherein the control circuitry is further configured to:
determine to allocate an entry in the cache circuitry for first data from a read operation that reads from the memory;
evict second data from the cache circuitry to the memory, to free the entry in the cache circuitry for the allocation;
perform the read operation to read the first data from the memory while providing the latency quality-of-service guarantee to the read operation and counting the read operation toward the rate limit for the first class of traffic;
perform a write operation of the evicted second data to the memory as the first class of traffic, while providing the latency quality-of-service guarantee to the write operation of the evicted second data, but without counting the write operation of the evicted second data toward the rate limit for the first class of traffic; and
store the read first data into the allocated entry in the cache circuitry;
wherein the control circuitry is configured to count one or more other write operations, to the memory and of the first class of traffic, toward the rate limit for the first class of traffic.
|