US 12,353,900 B2
System and method enabling software-controlled processor customization for workload optimization
Andrew Ward Beale, Irvine, CA (US); and David Strong, Irvine, CA (US)
Assigned to Unisys Corporation, Blue Bell, PA (US)
Filed by Unisys Corporation, Blue Bell, PA (US)
Filed on Mar. 8, 2021, as Appl. No. 17/194,478.
Prior Publication US 2022/0283838 A1, Sep. 8, 2022
Int. Cl. G06F 9/455 (2018.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01)
CPC G06F 9/45558 (2013.01) [G06F 9/30112 (2013.01); G06F 9/3851 (2013.01); G06F 9/4881 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45583 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system for defining and accessing registers comprising:
at least one virtual processor comprising information indicative of at least one compiler that is adapted to analyze at least a portion of an executable context defining at least one particular process to executed upon at least one virtual processor and responsively produce at least one instruction set indicative of a virtual execution register context customized to support the at least one executable process;
at least one virtual execution context memory comprising stored information defining a particular virtual processor state, wherein the information defining the particular virtual processor state is stored as register context information and paired memory context information in a specific portion of a first addressable memory and based, at least in part, upon the at least one instruction set, wherein the at least one virtual execution context memory is defined by software in a configurable random-access memory storage system at run-time to have the precise capacity based on the register context information and the paired memory context information that define the processor state; and
the at least one virtual processor comprising information stored in a specific portion of a second addressable memory, the stored information defining at least one base register pointer, wherein the at least one base register pointer comprises at least one memory address enabling the at least one virtual processor to access the specific portion of the first addressable memory storing the information defining the particular virtual processor state.