US 12,353,886 B1
Adjusting instruction execution for enhanced security
Fabrice Marinet, Chateauneuf-le-Rouge (FR); Florian Reneld Ghislain Caullery, Cannes (FR); Frederic Amiel, Nice (FR); and Anton Dumas, Odenas (FR)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 9, 2024, as Appl. No. 18/408,442.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01)
CPC G06F 9/3887 (2013.01) [G06F 9/30145 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for secure processing comprising:
a memory comprising instructions; and
a processor coupled to the memory and configured to:
obtain a plurality of instructions, wherein the plurality of instructions comprises a sequential order for execution of the plurality of instructions by the processor;
determine that two or more instructions of the plurality of instructions are capable of being fused;
determine that a random variable satisfies an instruction fusion condition; and
execute, based on determining that the two or more instructions of the plurality of instructions are capable of being fused and the random variable satisfies the instruction fusion condition, the two or more instructions of the plurality of instructions as a single fused instruction.