US 12,353,883 B2
Executing memory requests out of order
Mark Landers, Hertfordshire (GB); and Martin John Robinson, Hertfordshire (GB)
Assigned to Imagination Technologies Limited, Kings Langley (GB)
Filed by Imagination Technologies Limited, Kings Langley (GB)
Filed on Jan. 26, 2021, as Appl. No. 17/159,019.
Application 17/159,019 is a continuation of application No. 15/621,042, filed on Jun. 13, 2017, granted, now 10,929,138.
Claims priority of application No. 1610328 (GB), filed on Jun. 14, 2016.
Prior Publication US 2021/0157596 A1, May 27, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/38 (2018.01); G06F 9/30 (2018.01); G06F 12/0815 (2016.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01)
CPC G06F 9/3836 (2013.01) [G06F 9/30087 (2013.01); G06F 9/3834 (2013.01); G06F 12/0815 (2013.01); G06F 13/1689 (2013.01); G06F 9/3861 (2013.01); G06F 13/4013 (2013.01); G06F 2212/60 (2013.01); Y02D 10/00 (2018.01)] 17 Claims
OG exemplary drawing
 
1. An instruction scheduler for use in an on-chip cache of a processor formed on a chip with the on-chip cache, the instruction scheduler comprising:
a cache management unit arranged, in response to determining that a memory request generated in the processor refers to data that is not stored in the on-chip cache, to generate a memory request on a further level of a memory hierarchy; and
a re-order buffer module arranged to control an order in which memory requests generated in the processor are executed within the on-chip cache such that request entries may be picked out for execution in any order, and comprising a data structure arranged to store pending memory requests, and wherein data is received from the further level of the memory hierarchy in an order that is different from an order in which the corresponding memory requests are generated in the processor.