US 12,353,881 B2
Circuitry and methods for power efficient generation of length markers for a variable length instruction set
Thomas Madaelil, Austin, TX (US); Jonathan Combs, Austin, TX (US); Khary Alexander, Cedar Park, TX (US); Martin Licht, Round Rock, TX (US); and Vikash Agarwal, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,680.
Prior Publication US 2022/0100516 A1, Mar. 31, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/0875 (2016.01)
CPC G06F 9/30149 (2013.01) [G06F 9/30152 (2013.01); G06F 9/3016 (2013.01); G06F 9/382 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A hardware processor core comprising:
a decoder circuit to decode instructions into decoded instructions;
an execution circuit to execute the decoded instructions;
an instruction cache;
an instruction length decoder circuit;
a predecode cache comprising a predecode bit, for each section of multiple sections of instruction data, that indicates when that section is identified as a boundary of a variable length instruction;
storage for an incomplete decode table comprising a single bit, for each proper subset of the multiple sections of the instruction data, that indicates when that proper subset of the multiple sections has one or more invalid predecode bits in the predecode cache; and
a fetch circuit to, for an incoming address of the instruction data, perform a lookup in the instruction cache and the incomplete decode table, and, when there is a hit in the incomplete decode table that indicates a first proper subset of the multiple sections of the instruction data for the incoming address has the one or more invalid predecode bits in the predecode cache and a hit in the instruction cache for the instruction data at the incoming address, cause the instruction length decoder circuit to generate one or more predecode bits for the first proper subset of the multiple sections of the instruction data for the incoming address that has the one or more invalid predecode bits.