US 12,353,880 B2
One-time programmable (OTP) memory controller with a control circuit configured to assert a pre-load start signal and a pre-load end signal, related processing system, integrated circuit and method
Antonino Giuseppe Fontana, Lentini (IT); Giuseppe Guarnaccia, San Gregorio di Catania (IT); and Stefano Catalano, Catania (IT)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on May 30, 2023, as Appl. No. 18/325,519.
Claims priority of application No. 102022000012764 (IT), filed on Jun. 16, 2022.
Prior Publication US 2023/0409320 A1, Dec. 21, 2023
Int. Cl. G06F 9/30 (2018.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01)
CPC G06F 9/3004 (2013.01) [G06F 3/0653 (2013.01); G06F 9/30116 (2013.01); G06F 9/30189 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A One-Time Programmable (OTP) memory controller comprising:
a data register;
a given number K of shadow-registers, wherein the number K is smaller than a given number N of memory slots of an OTP memory area;
a communication interface configured to receive a read request requesting data of a memory slot; and
a control circuit configured to receive a preload start signal and a shadow-register preload enable signal, wherein the control circuit is configured to manage a preload phase and a data-read phase,
wherein, in response to the preload start signal, the control circuit is configured to perform the preload phase by:
determining a mapping between the given number K of shadow-registers and the given number N of memory slots,
determining, for each of the given number K of shadow-registers, whether a shadow-register is preloadable as a function of the shadow-register preload enable signal,
in response to determining that the shadow-register is preloadable, transferring the data from the memory slot mapped to the shadow-register, the respective memory slot being mapped to the shadow-register, and
once the shadow-register is preloaded based on the shadow-register preload enable signal, asserting a preload end signal and starting the data-read phase, and
wherein the control circuit is configured to perform the data-read phase by:
selecting a memory location indicated in the read request,
determining whether the selected memory location is mapped to the shadow-register,
in response to determining that the selected memory location is mapped to the shadow-register, selecting the shadow-register mapped to the selected memory location and determining whether the selected shadow-register has been pre-loaded,
in response to determining that the selected shadow-register has been pre-loaded, transmitting the data stored in the selected shadow-register via the communication interface,
in response to determining that the selected shadow-register has not been pre-loaded, transferring the data from a selected memory slot to the selected shadow-register and then transmitting the data stored in the selected shadow-register via the communication interface, and
in response to determining that the selected memory location is not mapped to the shadow-register, transferring the data from the selected memory slot to the data register and then transmitting the data stored in the data register via the communication interface.