US 12,353,878 B2
Apparatuses, methods, and systems for instructions for matrix multiplication instructions
Menachem Adelman, Haifa (IL); Robert Valentine, Kiryat Tivon (IL); Zeev Sperber, Zikhron Yaakov (IL); Amit Gradstein, Binyamina (IL); Simon Rubanovich, Haifa (IL); Sagi Meller, Zikhron Yaakov (IL); Christopher Hughes, Santa Clara, CA (US); Evangelos Georganas, San Mateo, CA (US); Alexander Heinecke, San Jose, CA (US); and Mark Charney, Lexington, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2021, as Appl. No. 17/359,519.
Prior Publication US 2022/0414182 A1, Dec. 29, 2022
Int. Cl. G06F 9/30 (2018.01)
CPC G06F 9/30036 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30025 (2013.01); G06F 9/30038 (2023.08)] 14 Claims
OG exemplary drawing
 
1. An apparatus comprising:
decode circuitry to decode a single instruction having fields for an opcode, an indication of a location of a first source operand, an indication of a location of a second source operand, and an indication of a location of a destination operand, wherein the opcode is to indicate that execution circuitry is to at least convert data elements of the first and second source operands from a first floating point representation to a second floating point representation, perform matrix multiplication with the converted data elements, and accumulate results of the matrix multiplication in the destination operand in the first floating point representation, wherein the first floating point representation is single precision floating point and the second floating point representation is a 19-bit floating-point representation; and
the execution circuitry to execute to the decoded instruction as specified by the opcode.