US 12,353,847 B2
Semiconductor device capable of performing in-memory processing
Seonwook Kim, Namyangju (KR); Wonjun Lee, Seoul (KR); and Changhyun Kim, Seongnam (KR)
Assigned to SK hynix Inc, Icheon (KR); and Korea University Research and Business Foundation, Seoul (KR)
Filed by SK hynix Inc., Icheon (KR); and Korea University Research and Business Foundation, Seoul (KR)
Filed on Aug. 12, 2021, as Appl. No. 17/401,201.
Claims priority of application No. 10-2020-0152938 (KR), filed on Nov. 16, 2020.
Prior Publication US 2022/0157371 A1, May 19, 2022
Int. Cl. G06F 7/544 (2006.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06F 15/78 (2006.01)
CPC G06F 7/5443 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 15/7821 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory cell array;
an address input circuit;
a command decoder configured to decode a signal provided from a command input circuit;
a data Input/Output (IO) circuit;
a processing control circuit including a register array storing a first address of an operand;
a processing circuit configured to provide a processing result by performing an operation on data provided from the memory cell array; and
a switch circuit configured to control a data path among the processing circuit, the data IO circuit, and the memory cell array,
wherein the processing control circuit determines whether a second address provided from the address input circuit corresponds to the first address stored in the register array, and
wherein the switch circuit controls the data path to connect the memory cell array to the processing circuit when the second address provided from the address input circuit corresponds to the first address stored in the register array.