US 12,353,818 B2
Optimizing method, device and non-transient computer readable medium for integrated circuit layout
Cheng-Chen Huang, Hsinchu (TW); and Chun-Chuan Kuo, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed on Aug. 3, 2022, as Appl. No. 17/880,342.
Claims priority of application No. 111102818 (TW), filed on Jan. 24, 2022.
Prior Publication US 2023/0237240 A1, Jul. 27, 2023
Int. Cl. G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 30/373 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01)
CPC G06F 30/398 (2020.01) [G06F 30/367 (2020.01); G06F 30/392 (2020.01); G06F 30/3308 (2020.01); G06F 30/373 (2020.01); G06F 30/394 (2020.01)] 19 Claims
OG exemplary drawing
 
1. An optimizing method for an integrated circuit layout, the optimizing method comprising:
identifying, from an integrated circuit design file, a plurality of power rails and a plurality of power domains corresponding to the plurality of power rails;
performing design rule check on a plurality of circuit units generated by placing and routing in the integrated circuit design file, so as to calculate a plurality of usable regions;
performing a simulation process on the circuit units for current and voltage analysis, so as to determine electromigration violation points corresponding to the plurality of power rails and related current information;
defining, according to the electromigration violation points and the current information, paths to be corrected on the power rails corresponding to the electromigration violation points;
replacing types of vias on the power rails that do not overlap with the paths to be corrected; and
correcting, according to the plurality of current directions and positions of the electromigration violation points, a number of vias on the power rails that overlap with the paths to be corrected, so as to reduce a number of the electromigration violation points.