US 12,353,815 B2
Method for chip integration
Yung Feng Chang, Hsinchu (TW); Yu-Jung Chang, Hsinchu County (TW); Tung-Heng Hsieh, Hsinchu County (TW); and Bao-Ru Young, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 31, 2022, as Appl. No. 17/828,648.
Prior Publication US 2023/0385505 A1, Nov. 30, 2023
Int. Cl. G06F 30/392 (2020.01)
CPC G06F 30/392 (2020.01) 20 Claims
OG exemplary drawing
 
1. A method for making an integrated circuit (IC), comprising:
inserting black boxes into a layout of the IC;
connecting the black boxes with a connectivity network;
inserting first dummy patterns in areas of the layout outside of the black boxes and the connectivity network; and
after the inserting of the first dummy patterns, replacing the black boxes with circuit macros that have one-to-one correspondence with the black boxes, wherein each of the circuit macros includes circuit patterns in a central area of the respective circuit macro and second dummy patterns surrounding the central area,
wherein at least one of the following operations is performed by an electronic design automation (EDA) tool:
the inserting of the black boxes,
the connecting of the black boxes,
the inserting of the first dummy patterns, and
the replacing of the black boxes with the circuit macros.